1. Field of the Invention
The present invention relates to a column redundancy circuit in a semiconductor memory which improve yields by means of substituting defective cells with redundant memory cells provided that defective memory cells are detected.
2. Background of the Related Art
As the semiconductor technology develops abruptly to increase a density of integrated circuits, so does the storage capacity of semiconductor memories. That means that large number of memory cells can be integrated to a memory chip. The chip is rejected once a single defective cell is found out of the memory cells, thereby having a low yield and poorness in effectiveness.
Therefore, a method of increasing yields is widely used by means of replacing defective cells by redundant cells which are ready to be substituted. This method is essentially accompanied by the problems such as the increased chip size due to the redundant components and additional tests for repairing the defective cells, which is hardly welcomed in ordinary logic circuits. Yet, the method of repairing defective cells prevails in the various fields of memory devices over 64 Kb DRAM's because the occupied area of redundant memory cells is relatively smaller than that of normal memory cell arrays.
FIG. 1 shows block diagram of a X-decoder, a Y-decoder and memory cell arrays of 64 Kb unit MATs.
Referring to FIG. 1, the memory cell array 101 is composed of 256(32.times.8) unit MATs, and each unit MAT has a storage capacity of 64 Kb.
A Y-decoder 103 generates a plurality of Y-selection signals by means of decoding a column address. A Y-selection signal from the Y-decoder is inputted to two memory cell arrays 101 and 102 to select a bit line designated by a decoded column address, respectively. That is, two bit lines are simultaneously selected by a decoded column address at both memory cell arrays 101 and 102.
X-decoders 104 and 105 drive a designated word line by means of decoding a row address as a row decoder. The memory cell arrays 101 and 102 are equipped with X-decoders 104 and 105 which select word lines, respectively. The X-decoders 104 and 105 are inputted with an identical row address and then select word lines from the memory cell arrays, respectively.
FIG. 2 shows memory cell arrays in FIG. 1 which are partially magnified wherein sixteen unit MATs MAT00 to MAT33 are included in the memory cell arrays.
Referring to FIG. 2, two redundant Y-selection signal lines RYS0 and RYS1 and two redundant word lines RWL0 and RWL1 show how they are connected to each unit MAT. A redundant Y-selection signal line RYSx is connected to every two MAT rows, while a redundant word line RWLx is connected to every two MAT columns.
Each unit MAT MAT00 to MAT33 has 256 normal word lines and 256 Y-selection signal lines, yet not shown in the drawing. A plurality of bit lines are selected by a single Y-selection signal line and, simultaneously, data of a plurality of bits are outputted by a single column address, if the semiconductor memory shown in FIG. 1 and FIG. 2 is a synchronous DRAM. This is so-called a burst mode which decides the number of bits of data signals outputted simultaneously by a column address.
FIG. 3 show a block diagram of a column redundancy circuit in semiconductor memories according to a related art.
Referring to FIG. 3, a row address signal of external address signals in a TTL level is transformed into CMOS level in a row address buffer 213 and then inputted to a row redundancy circuit 214 in which the information of the row address of a defective normal memory cell is stored.
The row redundancy circuit 214 produces a row address of a redundant memory cell in order to replace a defective memory cell with the redundant memory cell when the row address of the defective memory cell is inputted row redundant circuit 214. This means that a word line of the defective memory cell is repaired. The address generated during the repairing process of a defective word line includes a MAT selection signal for designating an unit MAT having a defective memory cell, as well as the address for designating the memory cell.
A MAT selection signal .alpha. outputted from the row redundancy circuit 214 is inputted to a column redundancy circuit 215. A column address out of external addresses in TTL level is transformed into CMOS level by an address buffer 211 and then inputted to a counter 212 which counts the burst length. The column address from the counter 212 is inputted to a column redundancy circuit 215 and an Y-predecoder 216.
In this case, the MAT selection signal .alpha. and the column address are inputted to the column redundancy circuit 215. The MAT selection signal .alpha. is the signal for repairing a defect cell on a row. Thus, the repairing process is carried out for the word line of the memory cell of which row has been repaired.
The column redundancy circuit 215 activates a column redundant signal .beta. in order to repair a defective column once a repairing process is required by means of analyzing the MAT selection signal .alpha. and the column address. The Y-predecoder 216 outputs a signal to an Y-decoder by means of pre-decoding the present inputted column address once the column redundant signal .beta. is activated. Then, instead of a normal Y-selection signal NYSx, the Y-decoder 217 outputs a redundant Y-selection signal RYSx which is activated by an activated column redundant enable signal .tau..
However, when the columns of the two memory cell arrays 101 and 102 as shown in FIG. 1 are to be repaired by the column redundancy circuit, it is hard to repair one of the memory cell arrays 101 and 102 independently because two unit MATs are selected by a single MAT selection signal .alpha. which has been outputted from the row redundancy circuit 214.
Once defectiveness of a memory cell array, the column redundancy circuit repairs a defective memory cell as well as a normal memory cell designated by an identical address. Accordingly, the column redundancy circuit repairing the columns of the selected two MATs has low efficiency in repairing the defective memory cells.
The efficiency in repairing the defective memory cells may be increased provided that each of the memory cell arrays is repaired independently by using an additional Y-decoder. Yet, another problem of the layout size of a chip is caused due to the division of the Y-decoder.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.